PCB Conductor Spacing Calculator (IPC-2221B)
How far apart two traces must sit depends less on the voltage than on where they live. Buried in the laminate, 500 V needs a quarter millimetre; the same nets on an uncoated outer layer need ten times that, and ten times more again in the thin air of a high-altitude installation. IPC-2221B Table 6-1 encodes exactly that, and a conformal coating buys most of the internal-layer advantage back.
Formula
| B1 | internal conductors, any altitude |
| B2 | external conductors, uncoated, sea level to 3050 m |
| B3 | external conductors, uncoated, above 3050 m |
| B4 | external conductors with a permanent polymer coating |
What this model assumes, and where it stops
Assumptions
- The voltage entered is the DC or peak AC working voltage between the two specific conductors, including any DC bias.
- The generic-standard environment: IPC-2221B is the base design rule, uncontrolled by a product safety standard.
- The coated column assumes a qualified permanent coating over both conductors and their gap. Solder mask alone does not qualify - it is neither thick nor pinhole-controlled enough.
- Voltage bands are read inclusively at their upper edge: exactly 50 V uses the 31-50 V row.
Limitations
- This is the generic printed-board rule, not a safety-standard compliance check. Where IEC 60664-1, IEC 62368-1 or a product standard applies, its creepage and clearance values govern and are usually larger - check the creepage and clearance page.
- The component-lead columns of Table 6-1 (A5 to A7) are deliberately not reproduced here: public reproductions of them disagree, and guessing at a safety table is worse than omitting it.
- IPC-9592B, the power-conversion derivative, is more conservative than this table for computer and telecom power products.
- The table knows nothing about pollution degree, condensation or contamination beyond its two altitude columns; a dirty or humid environment needs the IEC treatment instead.
- Above 10 kV this page refuses: the linear extrapolation is the standard's own rule, but at that level field grading and the product standard, not a spacing table, decide the design.
When you need a 3D field solution instead
Closed-form models like the one above hold on idealised geometry. These are the cases where they stop being good enough and a full 3D electromagnetic and thermal solution is the only way to get a trustworthy answer:
- Sharp corners and pointed pads concentrate the field and break down below the uniform-gap expectation the table encodes.
- Slots, cutouts and rout paths between conductors change the surface path entirely - a milled slot can shrink the needed board area several-fold.
- Potted or partially coated assemblies where the field crosses several dielectrics and concentrates at the interfaces.
- Repetitive fast transients from wide-bandgap switching, which age insulation in ways a static spacing rule does not capture.
Common questions
Do I use RMS or peak voltage for PCB spacing?
Peak. IPC-2221B spacing is dimensioned against the DC or peak AC voltage between the conductors, because breakdown cares about the instantaneous field, not the heating value. For 230 V RMS mains that means at least 325 V, plus whatever transient allowance your product standard adds on top.
Why are internal layers allowed so much less spacing than external ones?
Because the laminate seals them. An internal gap sees solid resin - no dust, no condensation, no surface tracking - so 500 V needs only 0.25 mm buried but 2.5 mm on a bare outer layer. Routing a critical high-voltage crossing on an inner layer is one of the cheapest insulation upgrades available, at the cost of inspectability.
Does solder mask count as conformal coating for the coated column?
No. The coated column assumes a qualified permanent polymer coating applied over the finished assembly with controlled thickness and pinhole coverage. Solder mask is thin, porous and not qualified as insulation, so bare-board rules apply under it. This is one of the most common spacing-review findings.
IPC-2221 or IEC 60664-1 - which one governs my design?
If a product safety standard applies - IEC 62368-1, 61800-5-1, 60601-1 and friends, all built on IEC 60664-1 - its creepage and clearance values govern, and they are usually larger because they add pollution degree, material CTI and overvoltage category. IPC-2221B is the generic board-design floor for circuits no safety standard covers, such as low-voltage functional isolation. When in doubt compute both; the creepage and clearance page here does the IEC side.
References
- IPC-2221B - Generic standard on printed board design - Table 6-1, electrical conductor spacing
- IPC-9592B - Requirements for power conversion devices - the more conservative derivative
- IEC 60664-1 - Insulation coordination - governs where a product safety standard applies