Microstrip Impedance Calculator
A surface trace over one reference plane. This uses Hammerstad and Jensen rather than the older IPC-2141 curve fit, which is quoted to better than 0.2% in Z0 across two decades of width-to-height ratio. Solve for width to hit a target impedance.
Choosing something to solve for makes Characteristic impedance an editable target and computes the chosen input from it.
Formula
| w, h | trace width and dielectric height (m) |
| t | copper thickness (m) |
| er | substrate relative permittivity (Dk) |
| e_eff | effective permittivity of the quasi-TEM mode |
| eta0 | impedance of free space, 376.730 ohm |
What this model assumes, and where it stops
Assumptions
- Quasi-TEM propagation: the cross-section is small against a wavelength.
- Static (low-frequency) solution - no dispersion, so Dk and Z0 do not change with frequency.
- Perfect conductors and a lossless, homogeneous, isotropic dielectric.
- Infinitely wide reference plane with no splits, voids or stitching gaps under the trace.
- A uniform, straight, infinitely long line - no bends, vias, stubs or terminations.
- Rectangular trace cross-section; real etched traces are trapezoidal.
- Solder mask is ignored - it typically lowers Z0 by 1 to 3 ohm on a 50 ohm line.
Limitations
- No dispersion. Above roughly 1 GHz on FR-4 the effective Dk creeps upward and this static value reads low.
- No conductor or dielectric loss, so there is no attenuation output. For loss budgets you need Dk and Df at your actual frequency.
- Surface roughness is not modelled. On standard-profile copper it adds meaningfully to loss above about 2 GHz, though it barely moves Z0.
- The thickness correction is a widening approximation, valid while t is small against both w and h.
- Solder mask, which is present on nearly every real board, is not included.
When you need a 3D field solution instead
Closed-form models like the one above hold on idealised geometry. These are the cases where they stop being good enough and a full 3D electromagnetic and thermal solution is the only way to get a trustworthy answer:
- Reference-plane splits, voids or antipads under the trace, which the infinite-plane assumption cannot see.
- Vias, layer transitions and connector launches, where the discontinuity dominates the impedance budget.
- Tight bends, taper transitions and length-matching serpentines.
- Anything above roughly 5 GHz, where dispersion, surface roughness and dielectric loss stop being negligible.
- Trace-to-trace coupling beyond a single adjacent pair, and coupling between layers.
- Etch-factor trapezoidal cross-sections, where the top and bottom widths differ enough to shift Z0 by several percent.
- Boards where the trace passes over a plane gap and you need to know the actual impedance excursion, not a nominal number.
Common questions
How wide is a 50 ohm trace on 1.6 mm FR-4?
About 3.05 mm with 1 oz copper and Dk 4.3, giving an effective Dk near 3.27 and a propagation delay of roughly 6.0 ns per metre. On a thin 0.2 mm core the same 50 ohm target needs only about 0.35 mm.
Does solder mask change the impedance?
Yes, typically lowering a 50 ohm microstrip by one to three ohms because it replaces some of the air above the trace with a higher-Dk material. This calculator does not model it, so treat the result as the bare-copper value.
Why does my board house measure a different impedance?
Etch factor is the usual culprit: real traces are trapezoidal, not rectangular, so the effective width is less than the drawn width. Laminate Dk also varies with resin content and frequency, and the static model here has no dispersion.
References
- Hammerstad & Jensen - Accurate Models for Microstrip Computer-Aided Design, IEEE MTT-S 1980
- Wadell - Transmission Line Design Handbook, Artech House 1991